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general description the MAX1191 is an ultra-low-power, dual, 8-bit, 7.5msps analog-to-digital converter (adc). the device features two fully differential wideband track-and-hold (t/h) inputs. these inputs have a 440mhz bandwidth and accept fully differential or single-ended signals. the MAX1191 delivers a typical signal-to-noise and dis- tortion (sinad) of 48.6db at an input frequency of 1.875mhz and a sampling rate of 7.5msps while con- suming only 12mw. this adc operates from a 2.7v to 3.6v analog power supply. a separate 1.8v to 3.6v supply powers the digital output driver. in addition to ultra-low operating power, the MAX1191 features three power-down modes to conserve power during idle peri- ods. excellent dynamic performance, ultra-low power, and small size make the MAX1191 ideal for applica- tions in imaging, instrumentation, and digital communi- cations. an internal 1.024v precision bandgap reference sets the full-scale range of the adc to ?.512v. a flexible reference structure allows the MAX1191 to use its inter- nal reference or accept an externally applied reference for applications requiring increased accuracy. the MAX1191 features parallel, multiplexed, cmos- compatible tri-state outputs. the digital output format is offset binary. a separate digital power input accepts a voltage from 1.8v to 3.6v for flexible interfacing to dif- ferent logic levels. the MAX1191 is available in a 5mm 5mm, 28-pin thin qfn package, and is specified for the extended industrial (-40? to +85?) temperature range. for higher sampling frequency applications, refer to the max1195?ax1198 dual 8-bit adcs. pin-compatible versions of the MAX1191 are also available. refer to the max1192 data sheet for 22msps, and the max1193 data sheet for 45msps. applications ultrasound and medical imaging iq baseband sampling battery-powered portable instruments low-power video wlan, mobile dsl, wll receiver features ultra-low power 12mw (normal operation: 7.5msps) 0.3? (shutdown mode) excellent dynamic performance 48.7db snr at f in = 1.875mhz 69dbc sfdr at f in = 1.875mhz 2.7v to 3.6v single analog supply 1.8v to 3.6v ttl/cmos-compatible digital outputs fully differential or single-ended analog inputs internal/external reference option multiplexed cmos-compatible tri-state outputs 28-pin thin qfn package evaluation kit available (order max1193evkit) MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 MAX1191 5mm x 5mm thin qfn top view ina+ exposed paddle ina- gnd clk gnd inb+ inb- v dd refp refn com refin pd0 pd1 d0 d1 d2 d3 a/b d4 d5 d6 d7 ov dd ognd gnd v dd v dd pin configuration ordering information 19-2836; rev 1; 9/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX1191eti-t -40 c to +85 c 28 thin qfn-ep* (5mm x 5mm) *ep = exposed paddle.
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 7.5mhz, c refp = c refn = c com = 0.33f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v ina+, ina-, inb+, inb- to gnd .................-0.3v to (v dd + 0.3v) clk, refin, refp, refn, com to gnd ...-0.3v to (v dd + 0.3v) pd0, pd1 to ognd .................................-0.3v to (ov dd + 0.3v) digital outputs to ognd .........................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 28-pin thin qfn (derated 20.8mw/ c above +70 c) ...1667mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity inl 0.15 1.00 lsb differential nonlinearity dnl no missing codes over temperature 0.13 1.00 lsb +25 c 4 offset error <+25 c 6 %fs gain error excludes refp - refn error 2 %fs dc gain matching 0.01 0.2 db gain temperature coefficient 30 ppm/ c offset (v dd 5%) 0.2 power-supply rejection gain (v dd 5%) 0.05 lsb analog input differential input voltage range v diff differential or single-ended inputs 0.512 v common-mode input voltage range v com v dd / 2 v input resistance r in switched capacitor load 720 k ? input capacitance c in 5pf conversion rate maximum clock frequency f clk 7.5 mhz channel a 5.0 data latency channel b 5.5 clock cycles dynamic characteristics (differential inputs, 4096 point fft) f in = 1.875mhz 47 48.7 signal-to-noise ratio (note 2) snr f in = 3.75mhz 48.6 db f in = 1.875mhz 47 48.6 signal-to-noise and distortion (note 2) sinad f in = 3.75 48.5 db
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 7.5mhz, c refp = c refn = c com = 0.33f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units f in = 1.875mhz 59 69 spurious-free dynamic range (note 2) sfdr f in = 3.75mhz 68.7 dbc f in = 1.875mhz 72.0 thi r d - h ar m oni c d i stor ti on ( n ote 2) hd3 f in = 3.75mhz -70.0 dbc intermodulation distortion imd f in1 = 1mhz at -7db fs, f in2 = 1.01mhz at -7db fs -66 dbc third-order intermodulation im3 f in1 = 1mhz at -7db fs, f in2 = 1.01mhz at -7db fs -70 dbc f in = 1.875mhz -68.0 -57.0 total harmonic distortion (note 2) thd f in = 3.75mhz -67.0 dbc small-signal bandwidth ssbw input at -20db fs 440 mhz full-power bandwidth fpbw input at -0.5db fs 440 mhz aperture delay t ad 1.5 ns aperture jitter t aj 1db snr degradation at nyquist 2 ps rms overdrive recovery time 1.5 full-scale input 2 ns internal reference (refin = v dd ; v refp , v refn , and v com are generated internally) refp output voltage v refp - v com 0.256 v refn output voltage v refn - v com -0.256 v com output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v differential reference output v ref v refp - v refn 0.512 v differential reference output temperature coefficient v reftc 30 ppm/ c maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma buffered external reference (v refin = 1.024v, v refp , v refn , and v com are generated internally) refin input voltage v refin 1.024 v com output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v differential reference output v ref v refp - v refn 0.512 v maximum refp/refn/com source current i source 2ma
parameter symbol conditions min typ max units maximum refp/refn/com sink current i sink 2ma refin input resistance >500 k ? refin input current -0.7 a unbuffered external reference (refin = gnd, v refp , v refn , and v com are applied refp input voltage v refp - v com 0.256 v refn input voltage v refn - v com -0.256 v com input voltage v com v dd / 2 v differential reference input voltage v ref v refp - v refn 0.512 v refp input resistance r refp measured between refp and com 4 k ? refn input resistance r refn measured between refn and com 4 k ? digital inputs (clk, pd0, pd1) clk 0.7 x v dd input high threshold v ih pd0, pd1 0.7 x ov dd v clk 0.3 x v dd input low threshold v il pd0, pd1 0.3 x ov dd v input hysteresis v hyst 0.1 v clk at gnd or v dd 5 digital input leakage current di in pd0 and pd1 at ognd or ov dd 5 a digital input capacitance dc in 5pf digital outputs (d7 d0, a/ b ) output voltage low v ol i sink = 200a 0.2 x ov dd v output voltage high v oh i source = 200a 0.8 x ov dd v tri-state leakage current i leak 5 a tri-state output capacitance c out 5pf power requirements analog supply voltage v dd 2.7 3.0 3.6 v digital output supply voltage ov dd 1.8 v dd v MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 7.5mhz, c refp = c refn = c com = 0.33f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units normal operating mode, f in = 1.875mhz at -0.5db fs, clk input from gnd to v dd 4.0 5.0 idle mode (tri-state), f in = 1.875mhz at - 0.5db fs, clk input from gnd to v dd 4.0 standby mode, clk input from gnd to v dd 2.2 ma analog supply current i dd shutdown mode, clk = gnd or v dd , pd0 = pd1 = ognd 0.1 5.0 a normal operating mode, f in = 1.875mhz at -0.5db fs, c l 10pf 1.0 ma idle mode (tri-state), dc input, clk = gnd or v dd , pd0 = ov dd , pd1 = ognd 0.1 5.0 standby mode, dc input, clk = gnd or v dd, pd0 = ognd, pd1 = ov dd 0.1 digital output supply current (note 3) i odd shutdown mode, clk = gnd or v dd , pd0 = pd1 = ognd 0.1 5.0 a timing characteristics clk rise to cha output data valid t doa 50% of c lk to 50% of d ata, fi g ur e 5 ( n ote 4) 1 6 8.5 ns clk fall to chb output data valid t dob 50% of c lk to 50% of d ata, fi g ur e 5 ( n ote 4) 1 6 8.5 ns clk rise/fall to a/ b rise/fall time t da/ b 50% of c lk to 50% of a/ b, fi g ur e 5 ( n ote 4) 1 6 8.5 ns pd1 rise to output enable t en pd0 = ov dd 5ns pd1 fall to output disable t dis pd0 = ov dd 5ns clk duty cycle 50 % clk duty-cycle variation 10 % wake-up time from shutdown mode t wake , sd (note 5) 20 s wake-up time from standby mode t wake , st (note 5) 5.5 s digital output rise/fall time 20% to 80% 2 ns interchannel characteristics crosstalk rejection f in,x = 1.875mhz at -0.5db fs, f in,y = 0.3mhz at -0.5db fs (note 6) -75 db amplitude matching f in = 1.875mhz at -0.5db fs (note 7) 0.03 db phase matching f in = 1.875mhz at -0.5db fs (note 7) 0.03 degrees electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 7.5mhz, c refp = c refn = c com = 0.33f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 6 _______________________________________________________________________________________ fft plot channel a (differential inputs, 8192-point data record) MAX1191 toc01 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 1.000747mhz f inb = 3.020553mhz a ina = a inb = -0.5db fs f inb hd3 hd2 fft plot channel b (differential inputs, 8192-point data record) MAX1191 toc02 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 1.000747mhz f inb = 3.020553mhz a ina = a inb = -0.5db fs f ina hd3 hd2 fft plot channel a (differential inputs, 8192-point data record) MAX1191 toc03 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 3.020553mhz f inb = 1.000747mhz a ina = a inb = -0.5db fs f inb hd3 hd2 fft plot channel b (differential inputs, 8192-point data record) MAX1191 toc04 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 3.020553mhz f inb = 1.000747mhz a ina = a inb = -0.5db fs f ina hd3 hd2 two-tone imd plot (differential inputs, 8192-point data record) MAX1191 toc05 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f in2 f in1 f clk = 7.500567mhz f in1 = 1.8mhz f in2 = 2.3mhz a in = -7db fs typical operating characteristics (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.) electrical characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, f clk = 7.5mhz, c refp = c refn = c com = 0.33f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) note 1: specifications +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. note 2: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5db fs referenced to the amplitude of the digital output. snr and thd are calculated using hd2 through hd6. note 3: the power consumption of the output driver is proportional to the load capacitance (c l ). note 4: guaranteed by design and characterization. not production tested. note 5: sinad settles to within 0.5db of its typical value. note 6: crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. ffts are performed on each channel. the parameter is specified as power ratio of the first and second channel fft test tone bins. note 7: amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and phase of the fundamental bin on the calculated fft.
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc _______________________________________________________________________________________ 7 fft plot channel a (single-ended inputs, 8192-point data record) MAX1191 toc06 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 1.000747mhz f inb = 3.020553mhz a ina = a inb = -0.5db fs f inb hd3 hd2 fft plot channel b (single-ended inputs, 8192-point data record) MAX1191 toc07 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 1.000747mhz f inb = 3.020553mhz a ina = a inb = -0.5db fs f ina hd3 hd2 fft plot channel b (single-ended inputs, 8192-point data record) MAX1191 toc09 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 3.020553mhz f inb = 1.000747mhz a ina = a inb = -0.5db fs f ina hd3 hd2 fft plot channel a (single-ended inputs, 8192-point data record) MAX1191 toc08 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f clk = 7.500567mhz f ina = 3.020553mhz f inb = 1.000747mhz a ina = a inb = -0.5db fs f inb hd3 hd2 two-tone imd plot (single-ended inputs, 8192-point data record) MAX1191 toc10 analog input frequency (mhz) amplitude (db) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 04.0 f in2 f in1 f clk = 7.500567mhz f in1 = 1.8mhz f in2 = 2.3mhz a in = -7db fs typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 8 _______________________________________________________________________________________ signal-to-noise ratio vs. analog input frequency MAX1191 toc11 analog input frequency (mhz) snr (db) 10 43 44 45 46 48 47 49 50 42 0100 channel a channel b signal-to-noise and distortion vs. analog input frequency MAX1191 toc12 analog input frequency (mhz) snr (db) 10 43 44 45 46 48 47 49 50 42 0 100 channel a channel b total harmonic distortion vs. analog input frequency MAX1191 toc13 analog input frequency (mhz) thd (db) 10 -80 -75 -70 -65 -55 -60 -50 -45 -85 0 100 channel a channel b spurious-free dynamic range vs. analog input frequency MAX1191 toc14 analog input frequency (mhz) sfdr (db) 10 50 55 60 65 75 70 80 85 45 0 100 channel a channel b typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc _______________________________________________________________________________________ 9 signal-to-noise ratio vs. analog input power MAX1191 toc15 analog input power (db fs) snr (db) -10 -5 -15 -25 -20 10 20 30 40 50 60 0 -30 0 f in = 2.017059mhz signal-to-noise and distortion vs. analog input power MAX1191 toc16 analog input power (db fs) sinad (db) -10 -20 10 20 30 40 50 60 0 -30 0 f in = 2.017059mhz total harmonic distortion vs. analog input power MAX1191 toc17 analog input power (db fs) thd (dbc) -10 -5 -15 -25 -20 -60 -70 -50 -40 -30 -30 0 f in = 2.017059mhz spurious-free dynamic range vs. analog input power MAX1191 toc18 analog input power (db fs) sfdr (dbc) -10 -5 -15 -25 -20 50 40 60 70 80 30 -30 0 f in = 2.017059mhz typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 10 ______________________________________________________________________________________ signal-to-noise ratio vs. sampling rate MAX1191 toc19 f clk (mhz) snr (db) 15 10 5 46 47 48 49 50 45 020 f in = 2.017059mhz signal-to-noise and distortion vs. sampling rate MAX1191 toc20 f clk (mhz) sinad (db) 15 10 5 46 47 48 49 50 45 020 f in = 2.017059mhz total harmonic distortion vs. sampling rate MAX1191 toc21 f clk (mhz) thd (dbc) 15 10 5 -75 -70 -65 -60 -55 -50 -80 020 f in = 2.017059mhz spurious-free dynamic range vs. sampling rate MAX1191 toc22 f clk (mhz) sfdr (dbc) 15 10 5 55 60 65 70 75 80 50 020 f in = 2.017059mhz typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 11 signal-to-noise ratio vs. clock duty cycle MAX1191 toc23 clock duty cycle (%) snr (db) 55 50 45 46 47 48 49 50 45 40 60 f in = 2.017059mhz signal-to-noise and distortion vs. clock duty cycle MAX1191 toc24 clock duty cycle (%) sinad (db) 55 50 45 46 47 48 49 50 45 40 60 f in = 2.017059mhz total harmonic distortion vs. clock duty cycle MAX1191 toc25 clock duty cycle (%) thd (dbc) 55 50 45 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -80 40 60 f in = 2.017059mhz spurious-free dynamic range vs. clock duty cycle MAX1191 toc26 clock duty cycle (%) sfdr (dbc) 55 50 45 62 64 66 68 70 72 74 76 78 80 60 40 60 f in = 2.017059mhz typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 12 ______________________________________________________________________________________ input bandwidth vs. analog input frequency MAX1191 toc31 analog input frequency (mhz) gain (db) 100 10 -8 -6 -4 -2 0 2 4 6 -10 1 1000 small-signal bandwidth -20db fs full-power bandwidth -0.5db fs v dd (v) 3.5 3.4 3.3 3.2 3.0 3.1 2.9 2.8 2.7 3.6 reference voltage vs. analog supply voltage MAX1191 toc32 v refp - v refn (v) 0.5105 0.5110 0.5115 0.5120 0.5125 0.5130 0.5100 v dd = v refin temperature ( c) 60 35 10 -15 -40 85 reference voltage vs. temperature MAX1191 toc33 v refp - v refn (v) 0.5105 0.5110 0.5115 0.5120 0.5125 0.5130 0.5100 v dd = v refin integral nonlinearity MAX1191 toc27 digital output code inl (lsb) 224 192 128 160 64 96 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0256 differential nonlinearity MAX1191 toc28 digital output code dnl (lsb) 224 192 128 160 64 96 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 offset error vs. temperature MAX1191 toc29 temperature ( c) offset error (% fs) 60 35 10 -15 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -40 85 v refin = 1.024v channel b channel a -0.05 0 0.05 0.10 0.20 0.15 0.25 0.30 -0.10 gain error vs. temperature MAX1191 toc30 temperature ( c) gain error (% fs) 60 35 10 -15 -40 85 v refin = 1.024v channel b channel a typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 13 supply current vs. input frequency MAX1191 toc34 f in (mhz) digital supply current (ma) analog supply current (ma) 3 2 1 0.5 0.6 0.7 0.8 0.9 0.4 3.9 4.0 4.1 4.2 4.3 3.8 04 digital supply current analog supply current supply current vs. sampling rate MAX1191 toc35 f clk (mhz) supply current (ma) 15 10 5 a: analog supply current (i dd ) - internal and buffered external reference modes b: analog supply current (i dd ) - unbuffered external reference mode c: digital supply current (i odd ) - all reference modes 2 4 1 3 5 6 7 0 020 a b c f in = 2.017059mhz pin description pin name function 1 ina- channel a negative analog input. for single-ended operation, connect ina- to com. 2 ina+ channel a positive analog input. for single-ended operation, connect signal source to ina+. 3, 5, 10 gnd analog ground. connect all gnd pins together. 4 clk converter clock input 6 inb+ channel b positive analog input. for single-ended operation, connect signal source to inb+. 7 inb- channel b negative analog input. for single-ended operation, connect inb- to com. 8, 9, 28 v dd converter power input. connect to a 2.7v to 3.6v power supply. bypass v dd to gnd with a combination of a 2.2f capacitor in parallel with a 0.1f capacitor. 11 ognd output driver ground 12 ov dd output driver power input. connect to a 1.8v to v dd power supply. bypass ov dd to gnd with a combination of a 2.2f capacitor in parallel with a 0.1f capacitor. 13 d7 tri-state digital output. d7 is the most significant bit (msb). 14 d6 tri-state digital output 15 d5 tri-state digital output 16 d4 tri-state digital output 17 a/ b channel data indicator. this digital output indicates channel a data (a/ b = 1) or channel b data (a/ b = 0) is present on the output. 18 d3 tri-state digital output 19 d2 tri-state digital output 20 d1 tri-state digital output 21 d0 tri-state digital output. d0 is the least significant bit (lsb). 22 pd1 power-down digital input 1. see table 3. typical operating characteristics (continued) (v dd = 3.0v, ov dd = 1.8v, v refin = v dd (internal reference), c l 10pf at digital outputs, differential input at -0.5db fs, f clk = 7.500567mhz at 50% duty cycle, t a = +25 c, unless otherwise noted.)
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 14 ______________________________________________________________________________________ detailed description the MAX1191 uses a seven-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel a and 5.5 clock cycles for channel b. at each stage, flash adcs convert the held input volt- ages into a digital code. the following digital-to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. the resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all stages. digital error correction compensates for adc comparator off- sets in each pipeline stage and ensures no missing codes. figure 2 shows the MAX1191 functional diagram. pin description (continued) pin name function 23 pd0 power-down digital input 0. see table 3. 24 refin reference input. internally pulled up to v dd . 25 com common-mode voltage i/o. bypass com to gnd with a 0.33f capacitor. 26 refn negative reference i/o. conversion range is (v refp - v refn ). bypass refn to gnd with a 0.33f capacitor. 27 refp positive reference i/o. conversion range is (v refp - v refn ). bypass refp to gnd with a 0.33f capacitor. ep exposed paddle. internally connected to pin 3. externally connect ep to gnd. ina+ ina- t/h digital error correction d0?7 flash adc t/h dac - + x2 1.5 bits stage 1 stage 2 stage 7 figure 1. pipeline architecture?tage blocks ina+ ina- dec / t/h inb+ inb- dec / t/h / reference system and bias circuits pipeline adc a com refin refn refp clk timing ov dd ognd multiplexer output drivers power control d0 d7 / / v dd gnd a/b pd0 pd1 pipeline adc b MAX1191 figure 2. MAX1191 functional diagram
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 15 input track-and-hold (t/h) circuits figure 3 displays a simplified functional diagram of the input t/h circuits. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully dif- ferential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the ampli- fier input, and open simultaneously with s1, sampling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differential volt- ages are held on capacitors c2a and c2b. the ampli- fiers charge capacitors c1a and c1b to the same s3b s3a com s5b s5a inb+ inb- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a ina+ ina- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b MAX1191 figure 3. internal t/h circuits
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 16 ______________________________________________________________________________________ values originally held on c2a and c2b. these values are then presented to the first stage quantizers and iso- late the pipelines from the fast-changing inputs. the wide input bandwidth t/h amplifiers allow the MAX1191 to track and sample/hold analog inputs of high frequen- cies (>nyquist). both adc inputs (ina+, inb+, ina-, and inb-) can be driven either differentially or single ended. match the impedance of ina+ and ina-, as well as inb+ and inb-, and set the common-mode voltage to midsupply (v dd /2) for optimum performance. analog inputs and reference configurations the MAX1191 full-scale analog input range is v ref with a common-mode input range of v dd /2 0.2v. v ref is the difference between v refp and v refn . the MAX1191 provides three modes of reference operation. the voltage at refin (v refin ) sets the reference oper- ation mode (table 1). in internal reference mode, connect refin to v dd or leave refin unconnected. v ref is internally generated to be 0.512v 3%. com, refp, and refn are low- impedance outputs with v com = v dd /2, v refp = v dd /2 + v ref /2, and v refn = v dd /2 - v ref /2. bypass refp, refn, and com each with a 0.33f capacitor. in buffered external reference mode, apply a 1.024v 10% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2 + v refin /4, and v refn = v dd /2 - v refin /4. bypass refp, refn, and com each with a 0.33f capacitor. bypass refin to gnd with a 0.1f capacitor. in unbuffered external reference mode, connect refin to gnd. this deactivates the on-chip reference buffers for com, refp, and refn. with their buffers shut down, these nodes become high-impedance inputs ( figure 4) and can be driven through separate, external reference sources. drive v com to v dd /2 10%, drive v refp to (v dd /2 +0.256v) 10%, and drive v refn to (v dd /2 - 0.256v) 10%. bypass refp, refn, and com each with a 0.33f capacitor. for detailed circuit suggestions and how to drive this dual adc in buffered/unbuffered external reference mode, see the applications information section. clock input (clk) clk accepts a cmos-compatible signal level. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the exter- nal clock, use a clock with low jitter and fast rise and fall times (<2ns). in particular, sampling occurs on the rising edge of the clock signal, requiring this edge to figure 4. unbuffered external reference mode impedance v refin reference mode >0.8 x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33f capacitor. 1.024v 10% buffered external reference mode. an external 1.024v 10% reference voltage is applied to refin. v ref is internally generated to be v refin /2. bypass refp, refn, and com each with a 0.33f capacitor. bypass refin to gnd with a 0.1f capacitor. <0.3v unbuffered external reference mode. refp, refn, and com are driven by external reference sources. v ref is the difference between the externally applied v refp and v refn . bypass refp, refn, and com each with a 0.33f capacitor. table 1. reference modes MAX1191 1.5v 1.25v 1.75v 62.5 a 0 a com refn refp 4k ? 4k ? 62.5 a
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 17 provide lowest possible jitter. any significant aperture jitter would limit the snr performance of the on-chip adcs as follows: where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the MAX1191 clock input operates with a v dd /2 voltage threshold and accepts a 50% 10% duty cycle (see typical operating characteristics ). system timing requirements figure 5 shows the relationship between the clock, ana- log inputs, a/ b indicator, and the resulting output data. channel a (cha) and channel b (chb) are simultane- ously sampled on the rising edge of the clock signal (clk) and the resulting data is multiplexed at the out- put. cha data is updated on the rising edge and chb data is updated on the falling edge of the clk. the a/ b indicator follows clk with a typical delay time of 6ns and remains high when cha data is updated and low when chb data is updated. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for cha and 5.5 clock cycles for chb. digital output data (d0?7), channel data indicator (a/ b b ) d0 d7 and a/ b are ttl/cmos-logic compatible. the digital output coding is offset binary (table 2, figure 6). the capacitive load on the digital outputs d0 d7 should be kept as low as possible (<15pf) to avoid large digital currents feeding back into the analog por- tion of the MAX1191 and degrading its dynamic perfor- mance. buffers on the digital outputs isolate them from snr ft in aj log = ? ? ? ? ? ? 20 1 2 t dob t cl t ch t clk t doa t da/b 5 clock-cycle latency (cha), 5.5 clock-cycle latency (chb) a/b chb d0 d7 d0b cha d1a chb d1b cha d2a chb d2b cha d3a chb d3b cha d4a chb d4b cha d5a chb d5b cha d6a chb d6b cha chb clk figure 5. system timing diagram figure 6. transfer function input voltage (lsb) -1 -126 -125 256 2 x v ref 1lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+1 -127 +126 +128 +127 -128 +125 (com) (com) offset binary output code (lsb) 0000 0000 0000 0001 0000 0010 0000 0011 1111 1111 1111 1110 1111 1101 0111 1111 1000 0000 1000 0001
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 18 ______________________________________________________________________________________ heavy capacitive loads. to improve the dynamic perfor- mance of the MAX1191, add 100 ? resistors in series with the digital outputs close to the MAX1191. refer to the max1193 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 100 ? series resistors. power modes (pd0, pd1) the MAX1191 has four power modes that are con- trolled with pd0 and pd1. four power modes allow the MAX1191 to efficiently use power by transitioning to a low-power state when conversions are not required (table 3). shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the MAX1191 and placing the outputs in tri-state. the wake-up time from shutdown mode is dominated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 20s. when operating in the unbuffered external refer- ence mode, the wake-up time is dependent on the external reference drivers. when the outputs transition from tri-state to on, the last converted word is placed on the digital outputs. in standby mode, the reference and clock distribution circuits are powered up, but the pipeline adcs are unpowered and the outputs are in tri-state. the wake- up time from standby mode is dominated by the 5.5s required to activate the pipeline adcs. when the out- puts transition from tri-state to on, the last converted word is placed on the digital outputs. differential input voltage (in+ - in-) differential input (lsb) offset binary (d7?0) output decimal code +127 (+ full scale 1 lsb) 1111 1111 255 +126 (+ full scale 2 lsb) 1111 1110 254 +1 1000 0001 129 0 (bipolar zero) 1000 0000 128 -1 0111 1111 127 -127 (- full scale + 1 lsb) 0000 0001 1 -128 (- full scale) 0000 0000 0 v ref 127 128 v ref 126 128 v ref 1 128 v ref 0 128 -v ref 1 128 -v ref 127 128 -v ref 128 128 table 2. output codes vs. input voltage pd0 pd1 power mode adc internal reference clock distribution outputs 0 0 shutdown off off off tri-state 0 1 standby off on on tri-state 1 0 idle on on on tri-state 1 1 normal operating on on on on table 3. power logic
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 19 in idle mode, the pipeline adcs, reference, and clock distribution circuits are powered, but the outputs are forced to tri-state. the wake-up time from idle mode is dominated by the 5ns required for the output drivers to start from tri-state. when the outputs transition from tri- state to on, the last converted word is placed on the digital outputs. in the normal operating mode, all sections of the MAX1191 are powered. applications information the circuit of figure 7 operates from a single 3v supply and accommodates a wide 0.5v to 1.5v input common- mode voltage range for the analog interface between an rf quadrature demodulator (differential, dc-cou- pled signal source) and a high-speed adc. furthermore, the circuit provides required sinad and sfdr to demodulate a wideband (bw = 3.84mhz), qam-16 communication link. r iso isolates the op amp output from the adc capacitive input to prevent ringing and oscillation. c in filters high-frequency noise. MAX1191 ina+ com ina- a v = 6v/v v com = v dd /2 v com = 0.5v to 1.5v v sig = 85mv p-p r iso 22 ? r iso 22 ? r11 600 ? r9 600 ? r2 300 ? operational amplifiers choose either of the max4452/max4453/max4454 single/ dual/quad +3v, 200mhz op amps for use with this circuit. connect the positive supply rail (v cc ) to 3v. connect the negative supply rail (v ee ) to ground. decouple v cc with a 0.1 f capacitor to ground. resistor networks resistor networks ensure proper thermal and tolerance matching. for r1, r2, and r3 use a network such as vishay's 3r model number 300192. for r4 r11, use a network such as vishay's 4r model number 300197. r10 600 ? r8 600 ? r5 600 ? r4 600 ? r7 600 ? r6 600 ? c in 5pf c in 5pf r1 600 ? r3 600 ? figure 7. dc-coupled differential input driver
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 20 ______________________________________________________________________________________ using transformer coupling an rf transformer (figure 8) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1191 for optimum performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step- up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. in general, the MAX1191 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for high input frequencies. in differential input mode, even-order harmonics are lower as both inputs (ina+, ina- and/or inb+, inb-) are bal- anced, and each of the adc inputs only requires half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica- tion. amplifiers such as the max4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. buffered external reference drives multiple adcs the buffered external reference mode allows for more control over the MAX1191 reference voltage and allows multiple converters to use a common reference. to drive one MAX1191 in buffered external reference mode, the external circuit must sink 0.7a, allowing one reference circuit to easily drive the refin of multiple converters to 1.024v 10%. MAX1191 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1-6-kk81 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1-6-kk81 ina- ina+ inb- inb+ com figure 8. transformer-coupled input drive MAX1191 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf inb+ inb- com ina+ ina- 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 figure 9. using an op amp for single-ended, ac-coupled input drive
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 21 figure 10 shows the max6061 precision bandgap ref- erence used as a common reference for multiple con- verters. the 1.248v output of the max6061 is divided down to 1.023v as it passes through a one-pole, 10hz, lowpass filter to the max4250. the max4250 buffers the 1.023v reference before its output is applied to the MAX1191. the max4250 provides a low offset voltage (for high gain accuracy) and a low noise level. unbuffered external reference drives multiple adcs the unbuffered external reference mode allows for pre- cise control over the MAX1191 reference and allows multiple converters to use a common reference. connecting refin to gnd disables the internal refer- ence, allowing refp, refn, and com to be driven directly by a set of external reference sources. max4250 3v 2 4 2 1.248v 3 5 10hz lowpass filter 1 15 ? 1 refin v dd MAX1191 n = 1 24 gnd 1.023v note: one front-end reference circuit provides 15ma of output drive and supports over 1000 MAX1191s. 3 0.1 f 0.1 f 3v 1 f 1% 20k ? 1% 90.9k ? 0.1 f 2.2 f 0.1 f refp 27 0.33 f refn 26 0.33 f com 25 0.33 f refin v dd MAX1191 n = 1000 24 gnd 0.1 f refp 27 0.33 f refn 26 0.33 f com 25 0.33 f max6061 figure 10. external buffered (max4250) reference drive using a max6062 bandgap reference
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 22 ______________________________________________________________________________________ figure 11 shows the max6066 precision bandgap ref- erence used as a common reference for multiple con- verters. the 2.500v output of the max6066 is followed by a 10hz lowpass filter and precision voltage-divider. the max4254 buffers the taps of this divider to provide the 1.75v, 1.5v, and 1.25v sources to drive refp, refn, and com. the max4254 provides a low offset voltage and low noise level. the individual voltage fol- lowers are connected to 10hz lowpass filters, which fil- ter both the reference-voltage and amplifier noise to a level of 3nv/ hz . the 1.75v and 1.25v reference volt- ages set the differential full-scale range of the associat- ed adcs at 0.5v. the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. with the outputs of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters sup- port as many as 160 MAX1191s. max4254 1/4 47 ? 3v 2 2 2.500v 3 1 1 refp v dd MAX1191 n = 1 27 gnd note: one front-end reference circuit supports up to 160 MAX1191s. 3 0.1 f 10 f 6v 1 f 1% 30.1k ? 1% 10.0k ? 0.1 f 2.2 f 330 f 6v 0.33 f 26 24 0.33 f refn refin refin 25 0.33 f com max6066 1.748v 1% 10.0k ? 1% 49.9k ? refp v dd MAX1191 n = 160 27 gnd 0.33 f 26 24 0.33 f refn 25 0.33 f com 1.47k ? max4254 47 ? 6 5 7 10 f 6v 330 f 6v 1.498v 1.47k ? 47 ? 9 10 8 10 f 6v 330 f 6v 1.248v max4254 1.47k ? 1m ? max4254 13 12 14 11 4 0.1 f uncommitted 1m ? 3v 1/4 1/4 1/4 figure 11. external unbuffered reference driving 160 adcs with max4254 and max6066
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 23 typical qam demodulation application quadrature amplitude modulation (qam) is frequently used in digital communications. typically found in spread-spectrum-based systems, a qam signal repre- sents a carrier frequency modulated in both amplitude and phase. at the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator fol- lowed by subsequent upconversion can generate the qam signal. the result is an in-phase (i) and a quadra- ture (q) carrier component, where the q component is 90 phase shifted with respect to the in-phase compo- nent. at the receiver, the qam signal is demodulated into analog i and q components. figure 12 displays the demodulation process performed in the analog domain using the MAX1191 dual-matched, 3v, 8-bit adc and the max2451 quadrature demodulator to recover and digitize the i and q baseband signals. before being dig- itized by the MAX1191, the mixed-down signal compo- nents can be filtered by matched analog filters, such as nyquist or pulse-shaping filters. the filters remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (snr) perfor- mance and minimizing intersymbol interference. grounding, bypassing, and board layout the MAX1191 requires high-speed board layout design techniques. refer to the max1193 evaluation kit data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, prefer- ably on the same side as the adc, using surface- mount devices for minimum inductance. bypass v dd to gnd with a 0.1f ceramic capacitor in parallel with a 2.2f bipolar capacitor. bypass ov dd to ognd with a 0.1f ceramic capacitor in parallel with a 2.2f bipolar capacitor. bypass refp, refn, and com each to gnd with a 0.33f ceramic capacitor. multilayer boards with separated ground and power planes produce the highest level of signal integrity. use a split ground plane arranged to match the physical location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc s package. connect the MAX1191 exposed backside paddle to gnd. join the two ground planes at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. the ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital sys- tems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from the sensitive analog traces of either channel. make sure to isolate the analog input lines to each respective con- verter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. 0 90 8 downconverter max2451 ina+ MAX1191 ina- inb+ inb- dsp post- processing a/b figure 12. typical qam receiver application
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 24 ______________________________________________________________________________________ static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the MAX1191 are measured using the end-point method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. offset error ideally, the midscale MAX1191 transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. gain error ideally, the full-scale MAX1191 transition occurs at 1.5 lsb below full-scale. the gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. dynamic parameter definitions aperture jitter figure 13 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 13). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n bits): snr db[max] = 6.02 n + 1.76 in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc s error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: enob sinad . . = -176 602 hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 13. t/h aperture timing
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc ______________________________________________________________________________________ 25 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 v 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. the intermodulation prod- ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2 f1). the individual input tone levels are at -7db fs. third-order intermodulation (im3) im3 is the power of the worst third-order intermodula- tion product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. the third-order intermodulation products are (2 x f1 f2), (2 x f2 f1). the individual input tone levels are at -7db fs. power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supplies are moved 5%. small-signal bandwidth a small -20db fs analog input signal is applied to an adc in such a way that the signal s slew rate does not limit the adc s performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. note that the track/hold (t/h) performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5db fs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. thd vvvvv v log = ++++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 1 chip information transistor count: 7925 process: cmos
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc 26 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l cc l k k l l
MAX1191 ultra-low-power, 7.5msps, dual 8-bit adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm

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